RXDIR=0, RXEXT=0, RFSI=0, RFEN0=0, RFDIR=0, RFSL=0, REFS=0, RXBIT0=0, RSHFD=0, RSCKP=0, RFEN1=0
I2S Receive Configuration Register
| REFS | Receive Early Frame Sync. 0 (0): Receive frame sync initiated as the first bit of data is received. 1 (1): Receive frame sync is initiated one bit before the data is received. |
| RFSL | Receive Frame Sync Length. 0 (0): Receive frame sync is one-word long. 1 (1): Receive frame sync is one-clock-bit long. |
| RFSI | Receive Frame Sync Invert. 0 (0): Receive frame sync is active high. 1 (1): Receive frame sync is active low. |
| RSCKP | Receive Clock Polarity. 0 (0): Data latched on falling edge of bit clock. 1 (1): Data latched on rising edge of bit clock. |
| RSHFD | Receive Shift Direction. 0 (0): Data received MSB first. 1 (1): Data received LSB first. |
| RXDIR | Receive Clock Direction. 0 (0): Receive Clock is external. 1 (1): Receive Clock generated internally. |
| RFDIR | Receive Frame Direction. 0 (0): Frame Sync is external. 1 (1): Frame Sync generated internally. |
| RFEN0 | Receive FIFO Enable 0. 0 (0): Receive FIFO 0 disabled. 1 (1): Receive FIFO 0 enabled. |
| RFEN1 | Receive FIFO Enable 1. 0 (0): Receive FIFO 1 disabled. 1 (1): Receive FIFO 1 enabled. |
| RXBIT0 | Receive Bit 0. 0 (0): Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or 12) of receive shift register (MSB aligned). 1 (1): Shifting with respect to bit 0 of receive shift register (LSB aligned). |
| RXEXT | Receive Data Extension. 0 (0): Sign extension turned off. 1 (1): Sign extension turned on. |